One conventional computer platform includes a plurality of processor cores and a single memory space that is shared among all of the processor cores. The processor cores may be coherently partitioned into a plurality of virtual computing domains, and managed by a virtualization program executed in the platform. The platform hardware maintains memory consistency for this single memory space.
Unfortunately, in this conventional arrangement, memory coherency bandwidth requirements lead to contention issues among the processor cores. This places a limit on the performance a platform can deliver, making it difficult to improve performance by increasing the number of cores.
In another conventional arrangement, the parameters of the computing domains, such as, the number of such domains and the processor cores assigned to them are implemented and statically enforced in hardware. As a result, modification of these parameters does not become completely effective unless a reset of the platform, involving reboot of the operating system, is executed.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly.